1. Field of the Invention
The present invention is related to a nonvolatile ferroelectric memory device, and more particularly, to a nonvolatile ferroelectric memory device and a method for driving the same.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off states. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 illustrates a hysteresis loop of a general ferroelectric memory. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory will be described with reference to the accompanying drawings.
FIG. 2 is a schematic diagram of a unit cell of a general nonvolatile ferroelectric memory device. As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected to the wordline and a source connected to the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected to a drain of the transistor T1 and a second terminal is connected to the plate line P/L.
In case where the related art nonvolatile ferroelectric memory device includes a plurality of main bitlines and a plurality of sub bitlines connected to the main bitlines, a main bitline load controller is arranged near a sensing amplifier.
FIG. 3A illustrates a timing diagram of a write mode operation of the related art ferroelectric memory and FIG. 3B illustrates a timing diagram of a read mode operation of the related art ferroelectric memory.
During the write mode, an externally applied chip enable signal CSBpad is activated from the high state to the low state. At the same time, if a write enable signal WEBpad is applied from the high state to the low state, the write mode starts. Subsequently, if an address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from the low state to the high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at the high state. To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value “1” is written in the ferroelectric capacitor. On the other hand, a low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described.
If an externally applied chip enable signal CSBpad is activated from the high state to the low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data Qs corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data Qns is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. In other words, if the data is destroyed, the “d” state is transited to an “f” state as shown in the hysteresis loop of FIG. 1. If the data is not destroyed, the “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in case that the data is destroyed while the logic value “0” is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data; to recover the original data, the plate line becomes inactive from the high state to the low state in a state that the high signal is applied to the corresponding wordline.
The aforementioned related art nonvolatile ferroelectric memory device has several problems. In a nonvolatile ferroelectric memory device of the related art, during the read mode, data destroyed in the active period after a cell is accessed are restored in the precharge period and during the write mode, new data are written in the precharge period after the cell accessed in the active period. Even though this method works well in a normal operation state, it can cause a great danger when a power supply is unstable. In other words, if the power supply is cut in the long active period, data destroyed by the read operation can not be restored and new data externally input can not be written in a cell either.